# Advanced Packaging Everything that happens after silicon fabrication to turn dies into usable chip modules. Old packaging just connected one die to a substrate with wires. Advanced packaging combines multiple dies (chiplets) plus [[HBM Integration|HBM memory]] into one module with dense interconnects. Core techniques include [[2.5D Packaging]], [[3D Packaging]], [[Hybrid Bonding]], TSVs (through-silicon vias), and fan-out. [[CoWoS]] is TSMC's implementation and the standard for today's AI GPUs. ## Why It Matters Now **AI demand is packaging-limited.** You can have wafers, but if you can't package logic plus HBM at scale, you can't ship accelerators. The bottleneck shifted from transistors to packaging. [[Chiplets]] are the new scaling path. Reticle limits and yield economics push designers to split large dies into smaller pieces, then stitch them together in the package. This makes advanced packaging essential, not optional. Packaging now determines bandwidth, latency, power efficiency, and thermals. Performance gains increasingly come from the package, not just the transistor node. ## Value Chain Three layers create investable opportunities: - [[OSATs]] build packages at scale (ASE, Amkor) - Tool makers sell the picks-and-shovels (BESI for [[Hybrid Bonding]], Kulicke & Soffa for thermo-compression) - Foundries/IDMs offer integrated packaging (Intel EMIB/Foveros, TSMC [[CoWoS]]) Related: [[Advanced Packaging Investment Thesis]], [[Chiplet Economics]], [[First Principles and Mental Models MoC]] --- #deeptech #semiconductors #firstprinciple