# CoWoS Chip-on-Wafer-on-Substrate. TSMC's [[2.5D Packaging]] platform that became the standard for AI accelerators. Places logic dies and [[HBM Integration|HBM stacks]] side-by-side on a silicon interposer, then mounts everything on an organic substrate. The interposer acts as a high-density wiring layer. It provides much shorter, faster connections between logic and memory than traditional package routing. This matters because AI workloads are bandwidth-hungry and latency-sensitive. CoWoS capacity became the bottleneck during the AI buildout. You could have leading-edge wafers sitting idle if packaging slots weren't available. This is why [[OSATs]] and foundries are racing to add advanced packaging capacity. ## Why It Won CoWoS hit the market early and scaled fast. TSMC integrated it tightly with their logic manufacturing. Customers designing for Nvidia H100s or similar chips had limited alternatives. Network effects and switching costs kept CoWoS as the default choice. Current bottleneck: interposer manufacturing and [[HBM Integration|HBM]] attachment yield. Both are precision processes that limit throughput. Related: [[Advanced Packaging]], [[Chiplets]], [[Advanced Packaging Investment Thesis]] --- #deeptech #semiconductors