CoWoS (Chip-on-Wafer-on-Substrate) is TSMC's 2.5D packaging technology. It's the dominant method for packaging AI accelerators today. How it works: logic dies and [[HBM]] stacks sit side-by-side on a silicon interposer, which provides ultra-dense interconnects between compute and memory. The interposer then mounts on a substrate that connects to the board. Why it matters: bandwidth. HBM needs massive data throughput to feed AI workloads. CoWoS provides the short, wide connections that make this possible. Traditional packaging can't hit these densities. The constraint: CoWoS capacity is tight. TSMC is the primary supplier, and buildout takes time. This is why [[Packaging Capacity Bottleneck]] is real. [[OSATs - Outsourced Semiconductor Assembly and Test]] like [[Amkor - AMKR]] and [[ASE Technology - ASX]] are racing to add similar advanced packaging capacity. Alternatives exist (EMIB from Intel, fan-out from others), but CoWoS is the current standard for high-end AI chips. Links: [[Advanced Packaging MOC]], [[What Is Advanced Packaging]], [[HBM and Package Integration]], [[Chiplets and Heterogeneous Integration]] --- #semiconductors #deeptech